As dynamic random access memory devices become more highly integrated, space available for each memory cell is reduced, and more particularly, the space available for each memory cell capacitor is reduced. The capacitance C of a memory cell capacitor is proportional to the surface area A of the opposing electrodes, and proportional to the dielectric constant .epsilon. of the dielectric layer between the opposing electrodes. The capacitance C of the memory cell capacitor is inversely proportional to the distance d between the opposing electrodes. These mathematical relationships are shown in the following formula: ##EQU1##
As the area available for a capacitor decreases with increasing integration densities, the surface area A of the opposing electrodes may be reduced thereby reducing the capacitance of the memory cell capacitor. Reductions in memory cell capacitance, however, may reduce the performance of the integrated circuit memory device. Accordingly, there exists a need to maintain a predetermined memory cell capacitance despite reductions in memory cell capacitor size.
Three basic techniques have been developed to increase memory cell capacitance without increasing the size of the memory cell capacitor. First, the dielectric layer between the opposing electrodes can be made thinner. Second, a dielectric material such as BST(Ba(Sr,Ti)O.sub.3) or PZT (Pb(Zr,Ti)O.sub.3) having a relatively high dielectric constant can be provided between the opposing electrodes. Third, the surface area of the opposing electrodes can be increased. The use of thinner capacitor dielectric layers, however, may result in increased leakage currents, and dielectric materials such as BST and PZT may not yet be commercially viable. Some progress, however, has been made by providing structures for increasing the surface area of the opposing electrodes without increasing the area occupied by the capacitor.
In particular, electrode surface areas have been increased by forming hemispherical grained (HSG) silicon layers on the surface of the lower capacitor electrode. As shown in FIG. 1, however, the use of hemispherical grained silicon layers may cause an increase in a ratio between a minimum capacitor capacitance (Cmin) and a maximum capacitance (Cmax) that is significantly lower than 1. In FIG. 1, the reference symbols .circle-solid., .box-solid., .tangle-solidup., .tangle-soliddn., and .diamond-solid. indicate the capacitances measured respectively at the top, center, bottom, left, and right portions of the capacitor.
As shown, the capacitance has a minimum value Cmin of about 45 pF when approximately -2 V is applied. The capacitance has a maximum value Cmax of approximately 60 pF to 65 pF when about 2 V is applied. The Cmin/Cmax ratio is thus about 0.72 (45/62.5), which is significantly less than 1. The operation of the capacitor may thus be unstable, and the reliability of the integrated circuit memory device may be reduced.
When forming a hemispherical grained silicon layer, it may be desirable to selectively form the hemispherical grained silicon layer on the electrodes without forming the HSG layer on the exposed portions of the insulating layer. It may also be desirable to reduce leakage current, and to increase the Cmin/Cmax ratio. Selective growth and reduced leakage current can be provided by increasing process margins. It may be difficult, however, to increase the Cmin/Cmax ratio.
The Cmin/Cmax ratio can be increased by controlling the doping concentrations of the upper and lower capacitor electrodes and by increasing the dopant concentration of the lower capacitor electrode having the hemispherical grained silicon layer. It may not be easy, however, to vary the dopant concentrations of the upper and lower electrodes of the capacitor because a plate-poly used for the upper electrode may also be used to provide a resistor in a peripheral circuit region. In addition, increasing the doping concentration of the lower electrode may influence a bit line contact resistance and a transistor.
A conventional method of forming a hemispherical grained silicon layer is discussed in the reference by Watanabe et al. entitled "Hemispherical Grained Silicon (HSG-Si) Formation On In-Situ Phosphorous Doped Amorphous-Si Using The Seeding Method." Solid State Device and Materials, 1992, pp. 422-424. In this reference, the hemispherical grained silicon layer is doped by direct ion implantation. The hemispherical grained silicon layer is formed by a seeding method.
As shown in FIG. 2, an insulating layer 12 is formed on a semiconductor substrate 10, and a contact hole 14 is formed in the insulating layer 12. Moreover, a memory cell access transistor can be formed on the substrate 10 prior to forming the insulating layer 12, and the contact hole through the insulating layer 12 can expose a source/drain region of the memory cell access transistor. A lower capacitor electrode 16 is formed on the insulating layer 12 and coupled to the semiconductor substrate 10 through the contact hole 14. The lower capacitor electrode 16 is formed from undoped amorphous silicon (a-Si).
Disilane (Si.sub.2 H.sub.6) molecules are then irradiated onto the surface of the lower capacitor electrode 16 at a temperature of approximately 580.degree. C. thereby forming HSG seeds 18 as shown in FIG. 3. These seeds 18 can be used to form a hemispherical grained silicon layer on the lower capacitor electrode 16. The structure is then annealed at the same temperature thus causing the seeds 18 to grow. The seeds 18 are then grown to form a hemispherical grained silicon layer 20 on the lower capacitor electrode 16 as shown in FIG. 4.
The lower capacitor electrode 16 and the HSG silicon layer 20, however, may be undoped. Both the lower capacitor electrode 16 and the HSG silicon layer 20 can be doped by implanting arsenic (As) onto the surface of the structure including the lower capacitor electrode 16, the insulating layer 12, and the HSG silicon layer 20. The lower capacitor electrode 16 and the HSG silicon layer 22 can thus be doped as shown in FIG. 5. More particularly, the implant energy can be approximately 70 kV and the implant dose can be on the order of 10.sup.16 ions/cm.sup.2.
As discussed above, the lower capacitor electrode and the HSG silicon layer can be doped simultaneously using an ion implant. The HSG silicon layer, however, may be damaged by the ion implant so that the quality of the HSG silicon layer on the sides of the lower capacitor electrode 16 may be lower than that on the top of the lower electrodes.